1. Field of the Invention
This invention relates to the layout of electronic circuits and more particularly to complex computer aided design layout and correction of rule violations in a design layout of, for example, an integrated circuit (IC) device or printed wiring board, in preparation for fabrication.
2. Description of the Relevant Art
Design of an electronic circuit, for example, an integrated circuit (IC), is a complicated and time-consuming process. FIG. 1 illustrates a typical design flow of an integrated circuit device from conception through the generation of a fabrication ready design layout. Generally, the design flow commences with defining the design specifications or requirements, such as required functionality and timing, as indicated at 110. The requirements of the design are implemented, for example, as a net-list or electronic circuit description, as indicated at 120. The implementation can be perfommed by, for example, schematic capture (drawing the design with a computer aided design tool) or more typically, utilizing a high-level description language such as VHDL, Verilog and the like. The implemented design may be simulated to verify design accuracy, as indicated at 130. Design implementation and simulation may be iterative processes. For example, errors found by simulation may be corrected by design implementation and re-simulated.
Once the design is verified for accuracy with simulation, a layout of the design is created, as indicated at 140. The design layout may describe the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication of the electronic circuit and is typically implemented as one or more design files encoding representations of the layers and geometries. The design layout is typically very tightly linked to overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances of the circuit, and the silicon area is used to realize a certain function. The detailed design layout may require a very intensive and time-consuming design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
During creation of the design layout, a place and route tool is often used to place geometries on various layers of the design layout and to connect or route the cells together. In modern semiconductor design technologies, many metal layers are used to implement interconnections throughout an integrated circuit. For some integrated circuits, one or more polysilicon (poly) layers, or even active areas, are also used to implement interconnections. During the routing process, when a wire or other feature on one layer needs to be connected to a wire or another feature on another layer, a geometry representing a cut in an insulating layer between the two layers, called a via, is added to the layout design. During fabrication, a cut will be made in the insulating layer and the space will be filled in with a conductor (e.g. metal) in order to connect the wires/features. The size and shape of the cut are defined by a geometry (via) drawn on a via layer during creation of the design layout. Vias may be used to connect from one metal or polysilicon layer to another metal or polysilicon layer. For example, a via may be used to connect a feature (i.e., a design geometry) on each of two metal layers. The lower one of the two layers may be referred to as the landing metal layer and the upper one of the two layers may be referred to as the covering layer.
Once the design layout is created, it is checked against a set of design rules in a design rule check (DRC) operation, as indicated at 150. The created design layout typically must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart various geometries on different layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule may be, for example, a minimum spacing amount between geometries on a single layer or a minimum overlap of a geometry on one layer over a geometry on another layer. Design rules are typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries may be specified for different sizes of geometries. DRC may be a time-consuming, iterative process that often requires manual manipulation and interaction by the designer. The designer may perform design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC-clean (violation-free) design.
Circuit extraction is performed after the design layout is completed and error free, as illustrated at 160. The extracted circuit may identify individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present between the layers. A layout versus schematic check (LVS) may be performed, as indicated at 170, where the extracted net-list is compared to the design implementation created at 120. LVS may ensure that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, etc., may be corrected in the design layout before proceeding to post-layout simulation, as indicated at 180. The post-layout simulation may be performed using the extracted net-list, which may provide an assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. Once post-layout simulation is complete and errors found by DRC are corrected, the design may be ready for fabrication and may be sent to a fabrication facility.
As electronic circuit densities increase and technology advances, for example, in deep sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout area and the manufacturability and reliability of the circuit. For example, the density of a layer may be increased, additional vias added to interconnection areas, and the like. Deep sub-micron designs typically have stringent design rules that are often not recognized or not properly handled by existing EDA tools, for example, automated place and route tools. Therefore, when creating a design layout at 140, for example, many design rule violations may be created that must be corrected. As circuit densities increase, some of these design rules may be defined asymmetrically. For example, a design rule for spacing between two geometries or for minimum overlap of one geometry over another may have different values depending on the direction or orientation of the geometries with respect to each other.
Most design technologies include via enclosure rules to ensure that both the landing metal and the covering metal enclose the via by a certain amount. In other words, such an enclosure rule ensures that each metal layer overlaps a via with a certain amount of extra metal to ensure that the via provides a good connection between the two metal layers once fabricated. The design rule specifying the extra amount of metal around each via may be referred to as a “metal enclosure of a via” design rule, and at times simply as a via enclosure design rule.
In a modern semiconductor design technology, especially for a deep sub-micron design, poly and metal layers which are used to implement connections through vias apply different via enclosure rules depending on the width of the metal or poly in the vicinity of the via. When a via is placed in a wide metal area, it may need more metal enclosure than that of a via which is placed in a narrower metal area. When a via is partially in wide metal area and partially in non-wide metal area, it may need different metal enclosure in each different area. In general, as the design technology advances, more and more width classes of metal features may be used in a design layout, and each metal width class, or range, may have different via enclosure design rules.
Nanometer technologies may also contain asymmetric via enclosure design rules. For example, in some technologies and associated design rules, an “end metal overlap of via” violation, sometimes referred to as an endlap violation, may occur when a via cut is located near the end of a metal path. In such technologies, the minimum amount that the metal must overlap the via may be greater on the side nearest the end of the metal path than the minimum amount that the metal must overlap the via on the other sides of the via, according to an associated design rule. In such cases, if the metal nearest the end of the metal path does not overlap the via on that side by this greater amount, an endlap violation may occur. Additionally, in technologies with multiple width classes for interconnect layers (e.g., poly and metal layers), different enclosure rules may apply to each width class. With advancing design technology, more and more width classes may be used in a design layout, each having one or more respective via enclosure design rules.
Asymmetric via enclosure design rules give designers more flexibility to use narrow metal paths to hold vias. They may also help in fabrication, because they may reduce the need for jogs in a design that are created when metal must enclose a via cut by a relatively large amount on all sides. However, it is difficult for conventional EDA tools to construct a design to meet these types of design rules, because most conventional EDA tools are two-dimensional programs that are good at treating objects in both dimensions simultaneously or symmetrically, but not asymmetrically. Therefore, after routing, some metal paths created by conventional EDA tools, typically routing tools, may violate asymmetric endlap design rules. A metal patch may be placed over an endlap rule violation to correct it, in many cases. However, unless carefully and often manually performed, patches may cause additional design rule violations. For example, a metal patch placed over the end of a metal path may cause a minimum metal spacing rule violation or a jog rule violation. Also, with existing tools, it may be difficult or impossible to determine the correct location, orientation and dimensions for such patches without time-consuming manual intervention by the designer.
Several examples of the creation and incidental correction of various endlap violations are illustrated in FIGS. 2A-2H and described herein. In a first example of an endlap violation, the metal surrounding the via shown in FIG. 2A violates both a minimum metal area rule and an end metal enclosure of a via (endlap) rule. To correct the minimum metal area violation, a conventional EDA tool may place a patch centered on the via as shown in FIG. 2B or as shown in FIG. 2C for vertical and horizontal routing directions respectively. In both of these cases, the metal patch may enclose the via asymmetrically, correcting the endlap violation automatically as an artifact of correcting the minimum metal area violation.
In another example involving both an endlap violation and a minimum area violation, a conventional EDA tool may not correct the minimum area violation by placing a patch centered on the via, due to the minimum spacing violation it may cause. Instead, the minimum area violation may be corrected by the EDA tool placing a patch only in one direction, as shown in FIG. 2D. In this case, the geometries may still violate the endlap design rule.
In yet another example, a minimum area violation may be corrected by a conventional EDA tool placing a patch centered on the via, as shown in FIG. 2E, but the area difference between the patch and original metal geometry may be too small to correct an endlap design rule violation for the same geometries.
In some cases, minimum metal area rules are not violated, because a via is overlapped by a long metal path as shown in FIG. 2F, but the geometries violate an endlap design rule. In these cases, a conventional EDA tool may not automatically correct the endlap violation.
Some metal paths may contain two via cuts near the end of the metal path. In these cases, the end metal overlapping both of the vias may not meet the asymmetrical via enclosure rule, as shown in FIG. 2G. FIG. 2G also illustrates a single via cut in a corner of a metal path that may also violate the endlap rule. In both of these cases, conventional EDA tools may not correct the endlap violations automatically.
Another corner case is illustrated in FIG. 2H. It is a four via array for which the surrounding metal does not violate the minimum area design rule. If an automated technique for correcting endlap violations is not be able to determine a patch direction because of the configuration of the array, this type of violation may be corrected manually.
As previously discussed, an EDA tool may generate the types of violations described above. For example, a routing tool may create them when narrow metal paths are used. Because routing tools may do much of their work as part of an automated flow, the number of endlap violations inadvertently generated may be huge. When these endlap violations happen to coincide with a minimum area violation, they may be corrected as a consequence of the correction of the area violations, in some cases. In other cases, they may not be corrected by an existing automated flow.
Because EDA tools are increasingly relied upon to create design layouts, and because conventional EDA tools do not prevent the creation of certain violations, thousands of violations can be created that must be corrected. Performing a DRC and manipulation of the design layout to correct these violations often requires manual interaction from the designer. Creation of a violation-free design layout becomes a critical, time-consuming process. Due to the complexity of the design and because the place and route design flow can be repeated throughout the design process, manually fixing violations may not be an affordable approach.